1. Field of the Invention
The present invention relates to a single-poly electrically-programmable read-only-memory (EPROM) cell and, more particularly, to a single-poly EPROM cell that does not incorporate oxide isolation and thereby avoids problems with leakage along the field oxide edge that can lead to degraded data retention.
2. Description of the Related Art
A single-poly electrically-programmable read-only-memory (EPROM) cell is a non-volatile storage device fabricated using process steps that are fully compatible with conventional single-poly CMOS fabrication process steps. As a result, single-poly EPROM cells are often embedded in CMOS logic and mixed-signal circuits.
FIGS. 1A-1C show a series of views that illustrate a conventional single-poly EPROM cell 100. FIG. 1A shows a top view of cell 100, FIG. 1B shows a cross-sectional view taken along line A-A′ of FIG. 1A, while FIG. 1C shows a cross-sectional view taken along line B-B′ of FIG. 1A.
A. Structure of Conventional EPROM Cell
As shown in FIGS. 1A-1C, EPROM cell 100 includes spaced-apart source and drain regions 114 and 116 respectively, which are formed in a p-type semiconductor material 112 such as a well or a substrate, and a channel region 118 which is defined between source and drain regions 114 and 116. Source 114 includes a source contact 115, and drain 116 includes a drain contact 117.
As further shown in FIGS. 1A-1C, cell 100 also includes an n-well 120 formed over p-type material 112. Field oxide 105 is formed over p-type material 112 to isolate source region 114, drain region 116, and channel region 118 from n-well 120, and also to isolate EPROM cell 100 from the electrical fields of adjacent devices.
N-well 120 of cell 100 further includes adjoining p+ and n+ contact regions 122 and 124 having n+ contact 123 and p+ contact 125 respectively. Conventional EPROM cell 100 also includes a p-type lightly-doped-drain (PLDD) region 126 which adjoins p+ contact region 122.
A rectangular control gate region 128 is defined in n-well 120 between PLDD region 126 and field oxide 105.
A rectangular floating gate oxide 130 is formed over channel region 118. A rectangular control gate oxide 132 is formed over control gate region 128. Floating gate oxide 130 and control gate oxide 132 are typically grown at the same time during fabrication of conventional EPROM cell 100. As a result, oxides 130 and 132 have substantially the same thickness, e.g. approximately 120Å for 0.5 micron technology, and 70Å for 0.35 micron technology.
A rectangular floating gate 134 is formed over floating gate oxide 130, control gate oxide 132, and a portion of field oxide 105.
B. Operation of Conventional EPROM Cell
During operation, conventional EPROM cell 100 is programmed by applying a first positive programming voltage of approximately 12 volts to contact regions 122 and 124, which are shorted together, and a second positive programming voltage of approximately 6-7 volts to drain region 116. In addition, both p-type material 112 and source region 114 are grounded.
When the positive first programming voltage is applied to contact regions 122 and 124, a positive potential is induced on floating gate 134. The positive potential induced on floating gate 134 causes an initial depletion region (not shown) to form in channel region 118, increasing the potential at the surface of channel region 118. Source region 114 then injects electrons into the surface of channel region 118 which, in turn, forms a channel of mobile electrons at the inversion layer.
The positive second programming voltage applied to drain region 116 sets up an electric field between source and drain regions 114 and 116 which then accelerates the electrons in the channel. The accelerated electrons then have ionizing collisions that form “hot channel electrons”. The positive potential of floating gate 134 attracts these hot channel electrons, which penetrate gate oxide layer 130 and begin accumulating in floating gate 134, thereby raising the threshold voltage of cell 100.
Conventional EPROM cell 100 is read by applying a first positive read voltage of approximately 5 volts to contact regions 122 and 124, and a second positive read voltage of approximately 1-2 volts to drain region 116. Both p-type material 112 and source region 114 remain grounded.
Under these read bias conditions, a positive potential is induced on floating gate 134 by the above-described mechanism which is (1) sufficient, i.e., larger than the threshold voltage of the cell, to create a channel current that flows from drain region 116 to source region 114 if cell 100 has not been programmed, and (2) insufficient, i.e., less than the threshold voltage of the cell, to create the channel current if cell 100 has been programmed.
The logic state of cell 100 is then determined by comparing the channel current with a reference current.
Conventional EPROM cell 100 is erased by irradiating cell 100 with ultraviolet (UV) light to remove the electrons. The UV light increases the energy of the electrons which, in turn, allows the electrons to penetrate the surrounding layers of oxide.
C. Disadvantages of Conventional EPROM Cell
One problem with the conventional single-poly EPROM cell 100 is that this cell design is prone to leakage of gate oxide over the edge of the field oxide. Specifically, Kooi et al. have discovered that a thin layer of silicon nitride can form in the silicon during oxidation, at the interface with the pad oxide. E. Kooi et al., J. Electrochem, Soc. 123,1117 (1976).
This phenomenon, referred to as the “Kooi effect,” occurs because NH3 or other nitrogen compounds generated by reaction between H2O and the masking nitride during field oxide formation may diffuse through the oxide and react with the silicon substrate. When a gate oxide is subsequently grown in silicon containing this nitride, oxide growth is impeded and the gate oxide is thinned. The resulting highly localized thin gate oxide portions can in turn give rise to problems of low-voltage breakdown of the gate oxide, resulting in leakage. Such gate oxide leakage is particularly problematic in the conventional EPROM cell described above, as the integrity of the voltage stored in the floating gate must remain unaffected over long periods of time.
Therefore, there is a need for a single-poly EPROM cell design that eliminates the field oxide edge as a potential source of leakage.
A second problem of the conventional EPROM cell 100 is the relatively large amount of surface area occupied by the device. As device sizes continue to shrink in response to market demand for greater packing densities, the dimensions of the EPROM cell must also be reduced. Thus, the amount of silicon surface area consumed by EPROM cell 100 looms as an increasingly serious problem.
Much of the surface area occupied by conventional EPROM cell 100 is due to the presence of p+ contact region 122 and PLDD region 126 in n-well 120. P+ contact region 122 and PLDD region 126 are essential to the operation of conventional EPROM cell 100 because of a prior unmasked threshold voltage adjustment implant (VTp) into the surface of n-well 120. The relationship between P+ contact region 122, PLDD region 126, and the VTp implant is now described in detail.
As discussed above, a conventional EPROM cell is programmed by applying a positive voltage to both n+ contact region 124 and p+ contact region 122. The positive voltage applied to n+ contact region 124 in conjunction with the potential of floating gate 134 draws electrons away from the surface of the n-well adjacent to control gate oxide 132.
Under the voltages typically used to program the conventional EPROM cell, the surface of n-well 120 is normally not rich enough in electrons to maintain accumulation because of a prior VTp implant of p-type dopant (typically Boron) into n-well 120. This prior VTp implant is unrelated to the function of the control gate region 128 of EPROM cell 100. Rather, this VTp implant is utilized to adjust the threshold voltages of p-channel MOS transistors. Because the VTp implant is not ordinarily masked during fabrication of conventional EPROM cell 100, p-type dopant (i.e. Boron) is introduced into the surface of n-well 120 as a side effect.
The prior VTp implant effectively reduces the available number of electrons in n-well 120 proximate to control gate region 128. Thus, as a result of the VTp implant, application of a typical positive programming voltage to n+ contact region 124 creates a depletion region 125 at the surface of control gate region 128.
Depletion region 125 interferes with capacitive coupling between control gate region 128 and floating gate 134. Specifically, since depletion region 125 is initially deep, the initial potential induced on floating gate 134 by control gate region 128 is reduced because the voltage applied to n+ contact region 124 is placed across both control gate oxide 132, and deep depletion region 125.
Because of the formation of the depletion region, earliest generation EPROM devices lacking p+ contact or PLDD regions in the n-well operated slowly, due to the time required for holes from thermally generated electron hole pairs to reduce the thickness of the initial deep depletion region. The resulting delay between the application of programming voltage and the appearance of sufficient programming bias upon the floating gate posed a serious drawback to these earlier devices.
P+ contact region 122, and PLDD region 126 are present in conventional EPROM cell 100 to mitigate the deleterious effect of depletion region 125 upon the capacitive coupling between control gate region 128 and floating gate 134. Specifically, the positive first programming voltage applied to p+ contact region 122 slightly forward-biases the p+ contact region to the surface of control gate region 128. As a result, p+ contact region 122 injects holes into the surface of control gate region 128, thereby inverting the surface of control gate region 128.
Holes injected by p+ contact region 122 quickly reduce the depth of depletion region 125 and form a hole inversion layer. No voltage drop occurs between n+ contact region 124 and the hole inversion layer formed underneath control gate oxide 132.
Without p+ contact region 122, few holes would accumulate at the surface of control gate region 128 upon initial depletion of the surface, because n-well 120 contains relatively few holes to begin with. Thus, the depth of the depletion region 125 could only be slowly reduced in size as thermally-generated holes drifted up to the surface of the control gate region 128.
Conventional EPROM cell 100 also requires the use of PLDD region 126. As is well known, the thickness of control gate oxide layer 132 at edge 132a adjacent to p+ contact region 122 is slightly thicker than at the central portion of gate oxide layer 132. As a result, the depletion region formed at edge 132a is too small to sufficiently invert the surface of n-well 120, which, in turn, limits the ability of p+ contact region 122 to inject holes into the surface of control gate region 128. Thus, conventional EPROM cell 100 utilizes PLDD region 126 to form a hole injection region that adjoins the surface region of control gate region 12B.
To summarize, the initial potential induced on floating gate 134 is defined by the voltage applied to contact regions 122 and 124, and by the thickness of control gate oxide 132 (which defines the coupling ratio between n-well 120 and floating gate 134). Application of a first positive programming voltage to n-well 120 causes an initially deep depletion region 125 to appear in the control gate region 128. P+ region 122 and PLDD region 126 allow for rapid reduction in the depth of the depletion region 125, and the formation of a hole inversion layer. This resulting hole inversion layer facilitates effective capacitive coupling between control gate region 128 and floating gate 134, permitting the full positive programming potential to be rapidly induced upon floating gate 134.
Conventional EPROM cell 100 is a functional device. However, p+ contact region 122 and PLDD region 126 occupy a significant amount of silicon surface area. Therefore, there is a need for an EPROM cell design that eliminates the p+ and PLDD structures while rapidly establishing strong enough capacitive coupling between the control gate region and the floating gate to program the floating gate.